10M16DAU324I6G FPGA Device: Features, Specifications, Advantages

• Low cost, small form factor packages—support multiple packaging technologies and pin pitches

• Multiple device densities with compatible package footprints for seamless migration between different device densities 

• RoHS6-compliant

• 4-input look-up table (LUT) and single register logic element (LE)

• LEs arranged in logic array block (LAB) 

• Embedded RAM and user flash memory

• Clocks and PLLs

• Embedded multiplier blocks 

• General purpose I/Os

• M9K—9 kilobits (Kb) memory blocks

• Cascadable blocks to create RAM, dual port, and FIFO functions

• User accessible non-volatile storage

• High speed operating frequency 

• Large memory size 

• High data retention 

• Multiple interface option

• One 18 × 18 or two 9 × 9 multiplier modes

• Cascadable blocks enabling creation of filters, arithmetic functions, and image processing pipelines

• 12-bit successive approximation register (SAR) type

• Up to 17 analog inputs 

• Cumulative speed up to 1 million samples per second ( MSPS) 

• Integrated temperature sensing capability

• Global clocks support

• High speed frequency in clock network

• Analog-based • Low jitter

• High precision clock synthesis

• Clock delay compensation

• Zero delay buffering

• Multiple output taps

• Multiple I/O standards support

• On-chip termination (OCT)

• Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitter

Supports up to 600 Mbps external memory interfaces:

• DDR3, DDR3L, DDR2, LPDDR2 (on 10M16, 10M25, 10M40, and 10M50.)

• SRAM (Hardware support only) 

Note: For 600 Mbps performance, –6 device speed grade is required. Performance varies according to device grade (commercial, industrial, or automotive) and device speed grade (–6 or –7). Refer to the Intel MAX 10 FPGA Device Datasheet or External Memory Interface Spec Estimator for more details.

• Internal configuratio

n• JTAG

• Advanced Encryption Standard (AES) 128-bit encryption and compression options

• Flash memory data retention of 20 years at 85 °C

• Single device integrating PLD logic, RAM, flash memory, digital signal processing (DSP), ADC, phase-locked loop (PLL), and I/Os

• Small packages available from 3 mm × 3 mm

• Sleep mode—significant standby power reduction and resumption in less than 1 ms

• Longer battery life—resumption from full power-off in less than 10 ms

• Intel Quartus® Prime Lite edition (no cost license)

• Platform Designer (Standard) system integration tool

• DSP Builder for Intel FPGAs

• Nios® II Embedded Design Suite (EDS)