Unclassified The 74LS107 is a JK Flip-Flop with individual J, K, Direct Clear, and Clock Pulse inputs. This article is going to explain datasheet, pinout, equivalent, applications, and other details about 74LS107 flip-flops.
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Nov 12, 2021
King Cocker
Introduction to JK flip flop
Unclassified
The 74LS107 is a JK Flip-Flop with individual J, K, Direct Clear, and Clock Pulse inputs. This article is going to explain datasheet, pinout, equivalent, applications, and other details about 74LS107 flip-flops.
74LS107A
The 74LS107 is a JK Flip-Flop with individual J, K, Direct Clear, and Clock Pulse inputs. The clock's HIGH-to-LOW transition is what triggers output adjustments. For predictable functioning, the J and K inputs must be steady one setup time before the high-to-low clock change. The 74LS107 IC offers a large operating voltage range, a wide operating temperature range, and directly interfaces with CMOS, NMOS, and TTL.
Logic Diagram
74LS107 Pinout
| Pin No | Pin Name | Description |
| 1 | J1 | Input Pin J1 |
| 2 | Q1 | Active high Output pin 1 |
| 3 | Q1′ | Active low output pin 1 |
| 4 | K1 | Input Pin K1 |
| 5 | Q2 | Active high Output pin 2 |
| 6 | Q2′ | Active low output pin 2 |
| 7 | GND | Ground Pin |
| 8 | J2 | Input Pin J2 |
| 9 | CP2 | Clock Pulse Input Pin 2 |
| 10 | CD2 | Reset Pin 2 |
| 11 | K2 | Input Pin K2 |
| 12 | CP1 | Clock Pulse Input Pin 1 |
| 13 | CD1 | Reset Pin 1 |
| 14 | VCC | Supply Voltage |
Technology Family: LS
Dual JK Flip Flop Package IC
-ve edge-triggered
VCC (Min): 4.75V
VCC (Max): 5.25
Bits (#): 2
Operating Voltage (Nom): 5V
Frequency at normal voltage (Max): 35MHz
Propagation delay (Max): 20ns
IOL (Max): 8mA
IOH (Max):-0.4mA
Rating: Catalog
Available in 14-pin PDIP, GDIP, PDSO packages
SIGNETICS CORP 74LS107A technical specifications, attributes, parameters and parts with similar specifications to SIGNETICS CORP 74LS107A.
SIGNETICS CORP 74LS107A technical specifications, attributes, parameters and parts with similar specifications to SIGNETICS CORP 74LS107A.
| Product Attribute | Attribute Value | |
|---|---|---|
| Surface Mount | NO | |
| Number of Terminals | 14Terminals | |
| Operating Temperature (Max.) | 70°C | |
| HTS Code | 8542.39.00.01 | |
| Terminal Position | DUAL | |
| Terminal Form | THROUGH-HOLE | |
| Number of Functions | 2Functions |
| Product Attribute | Attribute Value | |
|---|---|---|
| Supply Voltage | 5V | |
| JESD-30 Code | R-PDIP-T14 | |
| Qualification Status | Not Qualified | |
| Temperature Grade | COMMERCIAL | |
| Load Capacitance | 15pF | |
| Number of Bits | 2Bits | |
| Family | LS |
| Product Attribute | Attribute Value | |
|---|---|---|
| Output Polarity | COMPLEMENTARY | |
| Logic IC Type | J-K FLIP-FLOP | |
| Trigger Type | NEGATIVE EDGE | |
| Propagation Delay (tpd) | 30 ns | |
| Power Supply Current-Max (ICC) | 8mA | |
| fmax-Min | 30 MHz |
Two Independent JK Flip-Flops with Clock and Clear Inputs
Standard Pin Arrangement
Fast Switching Times
Operating Temperature up to 70°C
Standard TTL Switching Voltages
They are used in digital clocks, electronic meters, and other electronic devices that display numerical information.
SN7476, 74HC76, 74HC73a, 4027B
Advantages
The timing difficulty known as "RACE" is a downside of the JK flip-flop. RACE occurs when the output Q changes state before the clock input's timing pulse has a chance to move into the OFF state. To avoid timing issues, the timing pulse time (T) should be kept as short as possible.
Disadvantage
When both the inputs and clock pulse signal are at level 1 after the output is complemented once, output transmission will start getting repeated and continuous.
74LS107 Package Dimensions
Signetics was an American electronics manufacturer specifically established to make integrated circuits. Founded in 1961, they went on to develop several early microprocessors and support chips, as well as the widely used 555 timer chip. They were bought by Philips in 1975 and incorporated in Philips Semiconductors (now NXP).
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