Here shows a typical sample connection for the working of 74LS73 JK Flip-Flops.

74LS73 Circuit
The J and K pins are the Flip-input Flop's pins, while the Q and Q bar pins are its output pins. Through the use of a 1k resistor, input pins are brought down to the ground, preventing the pin from floating. When the button is not pressed, the pin is held to the ground, and when the button is pressed, the pin is held to supply voltage.
The reset button should be pulled up with a 1K resistor, and when grounded, the flip-flop will be reset. The JK flip-clock flop's signal is responsible for changing the output's state. Only the rising edge of the clock signal will cause the flip-flop to change its output.