8533AG-01 LVPECL Fanout Buffer: Pinout, Features and Datasheet

The following figure is the diagram of 8533AG-01 Pinout.

Pinout

The followings are 8533AG-01 Symbol, Footprint, and 3D Model.

PCB Symbol

PCB Footprint

3D Model

The 8533AG-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer. The 8533AG-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8533AG-01 ideal for those applications demanding well defined performance and repeatability.

This article provides you with a basic overview of the 8533AG-01 LVPECL Fanout Buffer, including its pin descriptions, features and specifications, etc., to help you quickly understand what 8533AG-01 is.

● Four differential 3.3V LVPECL outputs

● Selectable differential CLK, nCLK or LVPECL clock inputs

● CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

● PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL

● Maximum output frequency: 650MHz

● Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input

● Output skew: 30ps (maximum)

● Part-to-part skew: 150ps (maximum)

● Propagation delay: 1.4ns (maximum)

● Additive phase jitter, RMS: 0.06ps (typical)

● 3.3V operating supply

● 0°C to 70°C ambient operating temperature

● Lead-Free package

● Industrial temperature information available upon request

The following is the Block Diagram of 8533AG-01.

Block Diagram

The following diagram shows the 8533AG-01 Package.

Package

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