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HomeCommunitySubjectAD9520-0BCPZ Clock Generators: Pinout, Feature, Specification

AD9520-0BCPZ Clock Generators: Pinout, Feature, Specification

Clock Generator 64-Pin LFCSP EP Tray The AD9520-0BCPZ is IC CLOCK GEN 2.8GHZ VCO 64LFCSP, which is designed to work as Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers.

139

Jun 7, 2021

Abbott

AD9520-0BCPZ

568In Stock
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AD9520-0BCPZ Pinout

AD9520-0BCPZ Feature

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 2.53 GHz to 2.95 GHz Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input

Optional reference clock doubler

Reference monitoring capability

Automatic/manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references

Automatic recovery from holdover

Digital or analog lock detect, selectable

Optional zero delay operation

Twelve 1.6 GHz LVPECL outputs divided into 4 groups

Each group of 3 outputs shares a 1-to-32 divider with phase delay

Additive output jitter as low as 225 fs rms

Channel-to-channel skew grouped outputs < 16 ps

Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz)

Automatic synchronization of all outputs on power-up

Manual output synchronization available

SPI- and I²C-compatible serial control port

64-lead LFCSP

Nonvolatile EEPROM stores configuration settings

AD9520-0BCPZ Advantage

The AD9520-0BCPZ provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.

The AD9520-0BCPZ serial interface supports both SPI and I²C ports. An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for power-up and chip reset.

The AD9520-0BCPZ features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. If an application requires LVDS drivers instead of LVPECL drivers, refer to the AD9520-0BCPZ.

Each group of three outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase offset or coarse time delay to be set.

The AD9520-0BCPZ is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage of up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.

The AD9520-0BCPZ is specified for operation over the standard industrial range of −40°C to +85°C.

Specifications

Analog Devices Inc. AD9520-0BCPZ technical specifications, attributes, parameters and parts with similar specifications to Analog Devices Inc. AD9520-0BCPZ.

AD9520-0BCPZ Tech Specifications

Analog Devices Inc. AD9520-0BCPZ technical specifications, attributes, parameters and parts with similar specifications to Analog Devices Inc. AD9520-0BCPZ.

Product Attribute Attribute Value
Lifecycle StatusPRODUCTION (Last Updated: 3 weeks ago)
Factory Lead Time8 Weeks
Mounting TypeSurface Mount
Package / Case64-VFQFN Exposed Pad, CSP
Surface MountYES
Number of Pins64Pins
Frequency(Max)2.95GHz
Operating Temperature-40°C~85°C
PackagingTray
JESD-609 Codee3
Pbfree Codeno
Part StatusActive
Moisture Sensitivity Level (MSL)3 (168 Hours)
Number of Terminations64Terminations
ECCN CodeEAR99
TypeClock Generator, Fanout Distribution
Product Attribute Attribute Value
Terminal FinishTin (Sn)
Voltage - Supply3.135V~3.465V
Terminal PositionQUAD
Terminal FormNO LEAD
Peak Reflow Temperature (Cel)260
Supply Voltage3.3V
Terminal Pitch0.5mm
Frequency1.6GHz
Time@Peak Reflow Temperature-Max (s)30
Base Part NumberAD9520
OutputCMOS, LVPECL
Pin Count64
Number of Outputs12Outputs
Qualification StatusNot Qualified
Operating Supply Voltage3.3V
Number of Circuits1Circuit
Product Attribute Attribute Value
Logic FunctionClock
InputCMOS, LVDS, LVPECL
Ratio - Input:Output2:12, 2:24
Primary Clock/Crystal Frequency-Nom33.33MHz
PLLYes
Differential - Input:OutputYes/Yes
Max Duty Cycle50 %
Divider/MultiplierYes/No
Height950μm
Length9.1mm
Width9.1mm
REACH SVHCNo SVHC
RoHS StatusROHS3 Compliant
Lead FreeContains Lead
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AD9520-0BCPZ Functional Block Diagram

AD9520-0BCPZ Application

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710)

Clocking high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High-performance wireless transceivers

ATE and high-performance instrumentation

Broadband infrastructures

AD9520-0BCPZ Manufacture

Analog Devices (NASDAQ: ADI) is a world leader in the design, manufacture, and marketing of a broad portfolio of high performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits (ICs) used in virtually all types of electronic equipment. Since our inception in 1965, we have focused on solving the engineering challenges associated with signal processing in electronic equipment. Used by over 100,000 customers worldwide, our signal processing products play a fundamental role in converting, conditioning, and processing real-world phenomena such as temperature, pressure, sound, light, speed, and motion into electrical signals to be used in a wide array of electronic devices.

Datasheet PDF

Download datasheets and manufacturer documentation for Analog Devices Inc. AD9520-0BCPZ.

AD9520-0BCPZ Documents

Download datasheets and manufacturer documentation for AD9520-0BCPZ

Frequently Asked Questions

1.What happens if I run the part in an ambient environment which exceeds 85°C?
ADI does not guarantee specs on parts operating outside the temperature range listed in the product datasheet. The user may find that devices operate outside rated temperatures, but ADI does not recommend exceeding datasheet limits.
2.What is the difference between the coarse phase adjust and the fine delay adjust?
On the AD951x clock ICs, each output has a divider which features a coarse phase (or delay) adjust which allows for the selection of a given clock edge within the divide period as a delay or phase offset for that output. This feature adds no jitter to the clock output, but only allows for discrete delays in steps the size of the input clock period. However, certain outputs also have a feature called a fine delay adjust. This feature is only available on certain LVDS/CMOS outputs, and never on an LVPECL output.
3.What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
Harmonically related clocks in general do not produce extra jitter. However, the variation in propagation times can cause edges to occur noncoincidentally. This can possibly produce jitter if the amplitudes of the various edges are too high at a given node.
4.May I use the AD9540 for spread spectrum clocking?
The AD9540 is capable of doing a frequency sweep function which can be used for the EMI reduction technique called Spread Spectrum Clock Generation. A triangular waveform is easy to achieve using the frequency accumulator available on that product. Non-triangular waveforms can also be constructed using the profile registers to drive changes to the "Delta Frequency Tuning" word which is used by the frequency accumulator.
5.My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
Yes. It is very possible to turn off unused sections of the AD951x chips. There is a high degree of configuration which allows unused inputs, outputs, and the PLL to be powered off when not needed or not used. The programming register table shows the bits which control these power downs.
FAQ
1.What happens if I run the part in an ambient environment which exceeds 85°C?
ADI does not guarantee specs on parts operating outside the temperature range listed in the product datasheet. The user may find that devices operate outside rated temperatures, but ADI does not recommend exceeding datasheet limits.
2.What is the difference between the coarse phase adjust and the fine delay adjust?
On the AD951x clock ICs, each output has a divider which features a coarse phase (or delay) adjust which allows for the selection of a given clock edge within the divide period as a delay or phase offset for that output. This feature adds no jitter to the clock output, but only allows for discrete delays in steps the size of the input clock period. However, certain outputs also have a feature called a fine delay adjust. This feature is only available on certain LVDS/CMOS outputs, and never on an LVPECL output.
3.What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
Harmonically related clocks in general do not produce extra jitter. However, the variation in propagation times can cause edges to occur noncoincidentally. This can possibly produce jitter if the amplitudes of the various edges are too high at a given node.
4.May I use the AD9540 for spread spectrum clocking?
The AD9540 is capable of doing a frequency sweep function which can be used for the EMI reduction technique called Spread Spectrum Clock Generation. A triangular waveform is easy to achieve using the frequency accumulator available on that product. Non-triangular waveforms can also be constructed using the profile registers to drive changes to the "Delta Frequency Tuning" word which is used by the frequency accumulator.
5.My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
Yes. It is very possible to turn off unused sections of the AD951x chips. There is a high degree of configuration which allows unused inputs, outputs, and the PLL to be powered off when not needed or not used. The programming register table shows the bits which control these power downs.

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