◆ General
● External CAN FD Controller with Serial Peripheral Interface (SPI)
● Arbitration Bit Rate up to 1 Mbps
● Data Bit Rate up to 8 Mbps
● CAN FD Controller modes
- Mixed CAN 2.0B and CAN FD Mode
- CAN 2.0B Mode
● Conforms to ISO 11898-1:2015
◆ Message FIFOs
● 31 FIFOs, configurable as Transmit or Receive FIFOs
● One Transmit Queue (TXQ)
● Transmit Event FIFO (TEF) with 32 bit time stamp
◆ Message Transmission
● Message transmission prioritization:
- Based on priority bit field
- Message with lowest ID gets transmitted first using the Transmit Queue (TXQ)
● Programmable automatic retransmission attempts: unlimited, 3 attempts or disabled
◆ Message Reception
● 32 Flexible Filter and Mask Objects
● Each object can be configured to filter either:
- Standard ID + first 18 data bits, or
- Extended ID
● 32-bit Time Stamp
◆ Special Features
● VDD: 2.7 to 5.5V
● Active Current: maximum 20 mA at 5.5 V, 40 MHz CAN clock
● Sleep Current: 15 μA, typical
● Low Power Mode current: maximum 10 μA from –40°C to 150°C
● Message Objects are located in RAM: 2 KB
● Up to 3 Configurable Interrupt Pins
● Bus Health Diagnostics and Error Counters
● Transceiver Standby Control
● Start of frame pin for indicating the beginning of messages on the bus
● Temperature Ranges:
- Extended (E): –40°C to +125°C
- High (H): –40°C to +150°C
◆ Oscillator Options
● 40, 20 or 4 MHz Crystal or Ceramic Resonator; External Clock Input
● Clock Output with Prescaler
◆ SPI Interface
● Up to 20 MHz SPI clock speed
● Supports SPI Modes 0,0 and 1,1
● Registers and bit fields are arranged in a way to enable efficient access through SPI
◆ Safety Critical Systems
● SPI commands with CRC to detect noise on SPI interface
● Error Correction Code (ECC) protected RAM