PCM5100APWR Audio Stereo DAC: Diagram, Pinout, and Datasheet

The PCM5100APWR is a family of monolithic CMOS-integrated circuits in a tiny TSSOP package that includes a stereo digitalto-analog converter and accompanying support circuitry. To offer superior dynamic performance and better clock jitter tolerance, the PCM5100APWR devices leverage the latest iteration of TI's sophisticated segmentDAC architecture.

The PCM5100APWR  device produces 2.1-VRMS ground centered outputs using DirectpathTM charge-pump technology, allowing designers to avoid DC blocking capacitors on the output as well as extra muting circuits often associated with single supply line drivers.

By enabling loads as low as 1 k per pin, the integrated line driver outperforms all other chargepump-based line drivers, 

The device's internal PLL eliminates the need for a system clock (also known as master clock), allowing for a 3-wire  I2S  connection and lower system EMI.

For pop-free performance, the Intelligent Clock Error and PowerSense undervoltage protection use a two-level mute mechanism.

The PCM5100APWR series offers up to 20 dB lower out-of-band noise than many typical switched capacitor  DAC  architectures, decreasing EMI and aliasing in downstream amplifiers/ADCs (measured from traditional 100-kHz OBN measurements to 3 MHz).

The following figure is PCM5100APWR Pinout.

Pinout

The followings are PCM5100APWR Symbol, Footprint and 3D Model.

Symbol

Footprint

3D Model

• Ultra Low Out-of-Band Noise

• Integrated High-Performance Audio PLL with BCK Reference to Generate SCK Internally

• Direct Line Level 2.1-VRMS Output

• No DC Blocking Capacitors Required

• Line Level Output Down to 1KΩ

• Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120-dB Mute SNR

• Accepts 16-, 24-, and 32-Bit Audio Data 

• PCM Data Formats: I2S, Left-Justified

• Automatic Power-Save Mode When LRCK And BCK Are Deactivated 

• 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs

• Simple Configuration Using Hardware Pins 

• Single-Supply Operation: 14

– 3.3 V Analog, 1.8 V or 3.3 V Digital

• Qualified in Accordance with AEC-Q100 

The PCM5100APWR Functional Block Diagram is shown as follows.

Functional Block Diagram

The PCM5100APWR Typical Application is shown as follows.

Typical Application

• Hardware control

– Normal filter latency

– I2S digital audio interface

– Power rail monitoring from the system 12-V rail to mute system power loss early

• 2.1-VRMS single-ended analog outputs

• Single 3.3-V supply

• 3-wire I2S interface (BCK PLL)

The PCM5100APWR Simplified System Diagram is shown as follows.

Simplified System Diagram

• The PCM5100APWR device family is easy to set up. For a whole device, most engineers employ a shared common ground. AGND and DGND are both connected to GND.

• For best analog performance, keep digital clock and interface traces away from analog outputs with good system partitioning. Any high-speed clock return currents influencing the analog outputs are reduced as a result.

• The power supply and charge pump decoupling capacitors should be as close to the device as practicable.

• Signal routing should be done on the top layer, whereas GND can be done on the bottom layer.

Layout

• A/V Receivers, DVD, BD Players

• Automotive Infotainment and Telematics

• HDTV Receivers

• Aftermarket Automotive Amplifiers

The PCM5100APWR Package is shown as follows.

Package

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