SI5340 Clock Generator: Pinout, Features and Datasheet

The following figure is the diagram of SI5340 pinout.

Pinout

The followings are SI5340 Symbol, Footprint, and 3D Model.

PCB Symbol

PCB Footprint

3D Model

The any-frequency, any-output SI5340 clock generator combines a wide-band PLL with proprietary MultiSynth™ fractional synthesizer technology to offer a versatile and high performance clock generator platform. This highly flexible architecture is capable of synthesizing a wide range of integer and non-integer related frequencies up to 1 GHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter performance with 0 ppm error. Each of the clock outputs can be assigned its own format and output voltage enabling the Si5340 to replace multiple clock ICs and oscillators with a single device making it a true "clock tree on a chip." The Si5340 can be quickly and easily configured using ClockBuilderPro software. Custom part numbers are automatically assigned using a ClockBuilder Pro™ for fast, free, and easy factory pre-programming or the Si5340 can be programmed via I2C and SPI serial interfaces.

This article provides you with a basic overview of the SI5340 Clock Generator, including its pin descriptions, features and specifications, etc., to help you quickly understand what SI5340 is.

● Generates any combination of output frequencies from any input frequency

● Ultra-low jitter of 90 fs rms

● Input frequency range:

   ◆ External crystal: 25 to 54 MHz

   ◆ Differential clock: 10 to 750 MHz

   ◆ LVCMOS clock: 10 to 250 MHz

● Output frequency range:

   ◆ Differential: 100 Hz to 1028 MHz

   ◆ LVCMOS: 100 Hz to 250 MHz

● Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal                   amplitude

● Si5340: 4 input, 4 output, 44-QFN 7x7 mm

Silicon Labs SI5340A-D-GM technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI5340A-D-GM.

The following is the Block Diagram of SI5340.

Si5340 Detailed Block Diagram

● Clock tree generation replacing XOs, buffers, signal format translators

● Any-frequency clock translation

● Clocking for FPGAs, processors, memory

● Ethernet switches/routers

● OTN framers/mappers/processors

● Test equipment and instrumentation

● Broadcast video

The following diagram shows the SI5340 package.

44-QFN Package

The following is the Top Marking of SI5340.

Top Marking

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