SI5346 Clock Generator: Features, Pinout and Datasheet

The following figure is the diagram of SI5346 Pinout.

Pinout

The followings are SI5346 Footprint and 3D Model.

Footprint

3D Model

The SI5346 is a dual DSPLL version in a smaller package. Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on 4^th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5346 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up in a known configuration. Programming the Si5346 is easy with Silicon Labs' ClockBuilder Pro™ software. Factory preprogrammed devices are also available.

This article will introduce SI5346 systematically from its features, pinout to its specifications, applications, also including SI5346 datasheet and so much more.

● Four or two DSPLLs to synchronize to multiple inputs

● Generates any combination of output frequencies from any input frequency

● Ultra low jitter:

   ◆ 95 fs typ (12 kHz – 20 MHz)

● Input frequency range:

   ◆ Differential: 8 kHz to 750 MHz

   ◆ LVCMOS: 8 kHz to 250 MHz

● Output frequency range:

   ◆ Differential: up to 720 MHz

   ◆ LVCMOS: up to 250 MHz

● Flexible crosspoints route any input to any output clock

● Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 kHz

● Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude

● Status monitoring (LOS, OOF, LOL)

● Hitless input clock switching: automatic or manual

● Locks to gapped clock inputs

● Automatic free-run and holdover modes

● Fastlock feature for low nominal bandwidths

● Glitchless on-the-fly DSPLL frequency changes

● DCO mode: as low as 0.01 ppb steps per DSPLL

● Core voltage:

   ◆ V_DD: 1.8 V ±5%

   ◆ V_DDA: 3.3 V ±5%

● Independent output clock supply pins: 3.3, 2.5, or 1.8 V

● Output-output skew:

   ◆ Using same DSPLL: 65 ps (Max)

● Serial interface: I²C or SPI

● In-circuit programmable with non-volatile OTP memory

● ClockBuilder Pro software simplifies device configuration

● Si5346: Dual DSPLL, 44-QFN 7×7 mm

● Temperature range: –40 to +85 °C

● Pb-free, RoHS-6 compliant

Silicon Labs SI5346A-B-GM technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI5346A-B-GM.

The following is the Block Diagram of SI5346.

Si5346 Block Diagram

● OTN Muxponders and Transponders

● 10/40/100G network line cards

● GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)

● Carrier Ethernet switches

● Broadcast video

The following diagrams show the SI5346 Package.

View A

View B

The following diagram shows the SI5346 PCB Land Pattern.

PCB Land Pattern

The following is the Top Marking of SI5346.

Top Marking

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Download datasheets and manufacturer documentation for Silicon Labs SI5346A-B-GM.