SI5351C-B CMOS Clock Generator: Pinout, Features and Datasheet

The following figure is the diagram of SI5351C-B Pinout.

Pinout

The followings are SI5351C-B Symbol, Footprint, and 3D Model.

PCB Symbol

PCB Footprint

3D Model

The Si5351 is an I²C configurable clock generator that is ideally suited for replacing crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional divider architecture, the Si5351 can generate any frequency up to 200 MHz on each of its outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide variety of applications. The Si5351A generates up to 8 free-running clocks using an internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an internal VCXO and provides the flexibility to replace both free-running clocks and synchronous clocks. It eliminates the need for higher cost, custom pullable crystals while providing reliable operation over a wide tuning range. The Si5351C offers the same flexibility but synchronizes to an external reference clock (CLKIN).

This article will introduce SI5351C-B systematically from its features, pinout to its specifications, applications, also including SI5351C-B datasheet and so much more.

● Generates up to eight non-integerrelated frequencies from 2.5 kHz to 200 MHz

● I²C user definable configuration

● Exact frequency synthesis at each output (0 ppm error)

● Highly linear VCXO

● Optional clock input (CLKIN)

● Low output period jitter: < 70 ps pp, typ

● Configurable spread spectrum selectable at each output

● Operates from a low-cost, fixed frequency crystal: 25 or 27 MHz

● Supports static phase offset

● Programmable rise/fall time control

● Glitchless frequency changes

● Separate voltage supply pins provide level translation:

● Core VDD: 2.5 or 3.3 V

● Output VDDO: 1.8, 2.5, or 3.3 V

● Excellent PSRR eliminates external power supply filtering

● Very low power consumption

● Adjustable output delay

● Available in three packages types:

● 10-MSOP: 3 outputs

● 16-QFN (3x3 mm): 4 outputs

● 20-QFN (4x4 mm): 8 outputs

● PCIE Gen 1 compatible

● Supports HCSL compatible swing

The following is the Block Diagram of SI5351.

Si5351 Block Diagram

The following is the Functional Block Diagram of SI5351C.

Si5351C (20-QFN) Functional Block Diagram

● Audio/video equipment, gaming

● Printers, scanners, projectors

● Handheld Instrumentation

● Laser range finder

● Residential gateways

● Networking/communication

● Servers, storage

● XO replacement 

The following diagram shows the SI5351C-B Package Land Pattern.

20-Pin QFN Land Pattern

The following is the Top Marking of SI5351C-B.

20-Pin QFN Top Marking

Silicon Labs (NASDAQ: SLAB) is a leading provider of silicon, software and system solutions for the Internet of Things, Internet infrastructure, industrial control, consumer and automotive markets. Resolving the electronics industry's toughest problems, providing customers with significant advantages in performance, energy savings, connectivity, and design simplicity. Backed by world-class engineering teams with unsurpassed software and mixed-signal design expertise, Silicon Labs empowers developers with the tools and technologies they need to advance quickly and easily from initial idea to final product.